1. Field of the Invention
The present invention relates to digital circuitry designs of state machines, and more specifically, to systems, methods and computer products for efficiency improvements in the digital circuitry designs.
2. Description of Related Art
An electrical circuit with memory elements may be modeled using state equations and state variables to describe the behavior and state of the system. A complete set of state variables for a system, coupled with logic that defines the transitions between states, typically contains enough information about the system's history to enable computation of the system's future behavior. Simplifying the model to reduce the number of state variables, or simplifying the logic that defines state transitions, lessens the computational cost of analyzing the model, for example, to verify that it conforms to a given specification.
The synthesis and verification of state variable models often requires a great deal of computational resources. Hence, the ability to reduce design size is of central importance to a variety of tasks in logic design since verification algorithms often require exponential resources with respect to design size. The ability to reduce design size may make the difference in whether or not it is feasible to use a verification algorithm to expose a design flaw.
What is needed is an automated method of reducing design size while preserving the behavior of the design with respect to verification results.